1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly, to a VPP voltage generator of a semiconductor memory device.
2. Discussion of Related Art
In general, a semiconductor memory device generates a VPP voltage (VPP) higher than an external voltage (VDD) and applies the generated VPP voltage to several circuits of the semiconductor memory device such as a word line driver, a bit line isolation circuit and a data output buffer.
The VPP voltage can compensate for the loss of threshold voltages of transistors included in the internal circuits of the semiconductor memory device. More particularly, in a DRAM including a memory cell consisting of one cell capacitor and one cell transistor, a VPP voltage (VPP) higher than a voltage (VDD) when data are ‘1’ must be applied to the gate of the cell transistor in order to accurately store data in the memory cell.
FIG. 1 is a schematic block diagram of a VPP voltage generator in the related art. Referring to FIG. 1, the VPP voltage generator 10 includes an oscillator 11 and a pumping circuit 12.
The oscillator 11 periodically generates a pumping control signal (CTL) of a pulse form. The pumping circuit 12 generates a VPP voltage (VPP) through a charge pumping operation in response to the pumping control signal (CTL). The VPP voltage (VPP) is supplied to word lines when the word lines to which memory cells are connected are activated in a memory cell array (not shown) of a semiconductor memory device.
In a burst write operation, a burst read operation and a refresh operation of the operations of a semiconductor memory device such as DRAM, the amount of the VPP voltage (VPP) consumed is increased. In the VPP voltage generator 10, however, a cycle (i.e., an oscillation cycle) where the oscillator 11 generates the pumping control signal (CTL) is fixed to a set value. Therefore, there is a problem in that the VPP voltage generator 10 does not generate a VPP voltage (VPP) suitable for each operating mode of the semiconductor memory device. This problem serves to degrade the operational performance of the semiconductor memory device. This will be described below in more detail.
For example, a case where the oscillation cycle of the oscillator 11 is set to be short and the amount of the VPP voltage (VPP) consumed is reduced can be considered. In this case, the pumping circuit 12 performs an excessive charge pumping operation in response to the pumping control signal (CTL) that is frequently generated by the oscillator 11. As a result, as the VPP voltage (VPP) becomes unnecessarily high, a phenomenon in which the VPP voltage exceeds a target voltage (i.e., an overshoot phenomenon) occurs.
If the VPP voltage (VPP) is overshooted as described above, the voltage of an activated word line becomes unnecessarily high. Therefore, when the word line is disabled, a problem arises because a precharge time (tRP) of the word line is increased. There is also a problem in that the amount current consumed is increased due to an excessive charge pumping operation of the pumping circuit 12.
Meanwhile, a case where the oscillation cycle of the oscillator 11 is set to be long and the amount of the VPP voltage (VPP) consumed is increased can be taken into consideration. In this case, the pumping circuit 12 performs the charge pumping operation in response to the pumping control signal (CTL) that is rarely generated by the oscillator 11. As a result, as the VPP voltage (VPP) is lowered, a target voltage is lowered.
If the VPP voltage (VPP) is lower than the target voltage as described above, a voltage level of the word line does not sufficiently rise up to the VPP voltage (VPP) when the word line is activated. Therefore, charge sharing between bit lines is not smooth and development between bit lines is not properly performed accordingly. As a result, problems arise because a RAS-To-CAS Delay (tRCD) characteristic is lowered and I/O margin of data is short.
Furthermore, if the VPP voltage (VPP) is lower than a target voltage, there are problems in that a data retention time reduces and a refresh characteristic decreases in the refresh operation of the semiconductor memory device. There is also a problem in that the operational performance of the semiconductor memory device is lowered since the refresh operation speed is reduced.